Keynote

FinFETs: Novel Design Opportunities

Niraj K. Jha

Dept. of Electrical Engineering

Princeton University

 

The constant march of miniaturization of transistors with each new generation of bulk CMOS technology has resulted in significant improvements in digital circuit performance. Further scaling of bulk CMOS, however, faces significant challenges due to fundamental material and process technology limits, including short-channel effects, sub-threshold leakage, and device-to-device variations. It is expected that introduction of double-gate field-effect transistors, such as FinFETs, will be required to overcome these obstacles to scaling.

In this talk, we will explore the novel design opportunities from the circuit to architecture level made possible by the double-gate nature of FinFETs. Independent control of the front and back gates of FinFETs enables various new logic styles.  It also makes fine-grain leakage-delay tradeoffs possible.  This leads to circuits and architectures that are not feasible in bulk CMOS.  We will present several examples to show how the rich FinFET design space can be exploited.

Biography: Niraj K. Jha received his B.Tech. degree in Electronics and Electrical Communication Engineering from Indian Institute of Technology, Kharagpur, India in 1981 and Ph.D. degree in Electrical Engineering from University of Illinois at Urbana-Champaign in 1985.  He is a Professor of Electrical Engineering at Princeton University.  He is a Fellow of IEEE and ACM. He has co-authored four books, among which are “Switching and Finite Automata Theory, 3rd ed.” and “Testing of Digital Systems” that are being used around the world. He is the editor-in-chief of TVLSI and serves on the editorial boards of TCAD and four other journals. He is the co-author of 13 award-winning papers. His research interests include nanotechnology, embedded system analysis and design, power/thermal aware hardware/software design, computer-aided design of ICs and systems, computer security, and digital system testing.

 

 

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53rd IEEE International Midwest Symposium on Circuits and Systems