T3: Introduction to Asynchronous Circuits and NULL Convention Logic (NCL)
Presented by: Scott C. Smith and Jia Di
Abstract. The development of synchronous circuits currently dominates the semiconductor industry. However, major limiting factors to the synchronous, clocked approach include increasing power consumption, increasing difficulty of clock distribution, increasing clock rates, decreasing feature size, timing closure effort, and difficulty with design reuse. Asynchronous, clockless circuits require less power, generate less noise, and produce less electromagnetic interference (EMI), compared to their synchronous counterparts, without degrading performance. As demand increases for circuits with higher performance, greater complexity, and decreased feature size, the International Technology Roadmap for Semiconductors (ITRS) predicts a likely shift from synchronous to asynchronous design styles in order to increase circuit robustness, decrease power, and alleviate many clock-related issues. ITRS shows that asynchronous circuits accounted for 11% of chip area in 2008, compared to 7% in 2007, and estimates they will account for 23% of chip area by 2014, and 35% of chip area by 2019, which is a substantial portion of this multibillion dollar industry.
To meet this growing industry need, chip designers should familiarize themselves with asynchronous design to make themselves more marketable and more prepared for the challenges faced by the digital design community for years to come. This tutorial will provide an introduction to asynchronous logic, by comparing competing asynchronous paradigms to each other and to the synchronous paradigm. It will then focus on delay-insensitive asynchronous circuit design using NULL Convention Logic (NCL). Specifically, combinational circuit design, throughput optimization, and ultra-low power techniques will be detailed.
Participants need not have any prior knowledge of asynchronous circuit design, but should be familiar with basic logic design concepts, such as Boolean algebra and Karnaugh maps. At the end of this tutorial, participants will be familiar with the advantages of asynchronous circuits, the challenges to asynchronous design being integrated into the mainstream semiconductor design industry, and will be able to design optimized NCL circuits and systems.
Scott Christopher Smith
Associate Professor and Interim Associate Department Head of Electrical Engineering
University of Arkansas, Fayetteville, AR 72701
University of Central Florida Computer Engineering Ph.D. 2001
University of Missouri – Columbia Electrical Engineering M.S. 1998
University of Missouri – Columbia Computer Engineering B.S. 1996
University of Missouri – Columbia Electrical Engineering B.S. 1996
Associate Professor, Department of Computer Science and Computer Engineering, University of Arkansas, Fayetteville, AR 72701
University of Central Florida, Orlando, FL, PhD, 2004
Tsinghua University, Beijing, P. R. China, MSc, 2000
Tsinghua University, Beijing, P. R. China, BSc, 1997
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53rd IEEE International Midwest Symposium on Circuits and Systems