MWSCAS 2010

Tutorial T4

 

T4: Power-Aware Testing and Test Strategies for Low-Power Devices

Presented by: Patrick Girard, Nicola Nicolici, and  Xiaoqing Wen

 

Abstract.  Managing the power consumption of circuits and systems is now considered as one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low-power devices. This tutorial provides the fundamental and advanced knowledge in this area. It is organized into three main parts. The first one gives necessary background and discusses issues arising from excessive power dissipation during manufacturing test. The second part provides comprehensive knowledge of structural and algorithmic solutions that can be used to alleviate such problems.

The last part surveys low-power design techniques and shows how low-power circuits and systems can be tested safely without affecting yield and reliability. Electronic Design Automation (EDA) solutions for testing low-power devices are also covered in the last part of the tutorial.

 

Patrick GIRARD received a M.S. degree in Electrical Engineering and a Ph.D. degree in Microelectronics from the University of Montpellier, France, in 1988 and 1992 respectively. He is currently Research Director at CNRS (French National Center for Scientific Research), and Head of the Microelectronics Department of the LIRMM (Laboratory of Informatics, Robotics and Microelectronics of Montpellier -France). His research interests include all aspects of digital testing and memory testing, with emphasis on critical constraints such as timing and power. From 2006 to 2010, Patrick Girard was Vice-Chair of the European Test Technology Technical Council (ETTTC) of the IEEE Computer Society. He has served on numerous conference committees including ACM/IEEE Design Automation Conference (DAC), ACM/IEEE Design Automation and Test in Europe (DATE), IEEE International Test Conference (ITC), IEEE International Conference on Computer Design (ICCD), IEEE VLSI Test Symposium (VTS), IEEE European Test Symposium (ETS), IEEE Asian Test Symposium (ATS), and ACM/IEEE International Symposium on Low Power Electronic Design (ISLPED). Patrick Girard is the founder and Editor-in-Chief of the ASP Journal of Low Power Electronics (JOLPE). He is Associate Editor of the IEEE Transactions on VLSI Systems and the Journal of Electronic Testing–Theory and Applications JETTA - Springer. From 2005 to 2009, he was an Associate Editor of the IEEE Transactions on Computers. He is a co-editor of the book “Power-Aware Testing and Test Strategies for Low Power Devices”, Springer, 2009, and a co-author of the book “Advanced Test Methods for SRAMs – Effective Solutions for Dynamic Fault Detection in Nanoscale Technologies”, Springer, 2009. Patrick Girard has been involved in several European research projects (ESPRIT III ATSEC, EUREKA MEDEA, MEDEA+ ASSOCIATE, IST MARLOW, MEDEA+ NanoTEST, CATRENE TOETS) and has managed industrial research contracts with major companies like Infineon Technologies, Atmel, STMicroelectronics, etc. He has supervised 22 PhD dissertations and has published 6 books or book chapters, 34 journal papers, and more than 110 conference and symposium papers on these fields. He received two Best Paper Awards (ETS 2004 and DDECS 2005). Patrick Girard is a Senior Member of IEEE.

Nicola NICOLICI is an Associate Professor in the Department of Electrical and Computer Engineering at McMaster University, Canada. He received the Dipl. Ing. degree in Computer Engineering from the “Politehnica” University of Timisoara, Romania (1997), and a Ph.D. in Electronics and Computer Science from the University of Southampton, U.K. (2000). His research interests are in the area of computer-aided design and test. He has authored over seventy research papers and one book in this area and received the IEEE TTTC Beausang Award for the Best Student Paper at the International Test Conference (ITC 2000) and the Best Paper Award at the IEEE/ACM Design Automation and Test in Europe Conference (DATE 2004). He served on the technical program committees for DATE, IEEE/ACM Design Automation Conference (DAC), IEEE European Test Symposium (ETS), IEEE Defect and Fault Tolerance Symposium (DFT), IEEE Asian Test Symposium (ATS), IEEE International Conference on Computer Design (ICCD), IEEE/ACM International Symposium on Networks-on-Chip (NOCS), IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), IEEE Workshop on Silicon Debug and Diagnosis (SDD), and he served as the Co-Founder, Program Co-Chair and General Chair for the Diagnostic Services in Network-on-Chips Workshop. He was the guest co-editor for a special issue on Silicon Debug and Diagnosis (published by IET Proceedings on Computers and Digital Techniques in November 2007) and a special issue on Low Power Test (published by for the Journal of Electronic Testing – Theory and Applications in August 2008). He currently serves on the Editorial Boards of JETTA, IET Computers and Digital Techniques and Integration, the VLSI Journal. He is a member of the ACM SIGDA, the IET and the IEEE Computer and Circuits and Systems Societies.

Xiaoqing WEN received a B.E. degree from Tsinghua University, Beijing, China, in 1986, a M.E. degree from Hiroshima University, Hiroshima, Japan, in 1990, and a Ph.D degree from Osaka University, Osaka, Japan, in 1993. From 1993 to 1997, he was a Lecturer at Akita University, Akita, Japan. He was a Visiting Researcher at University of Wisconsin, Madison, U.S.A., from October 1995 to March 1996. He joined SynTest Technologies, Inc., U.S.A., in 1998, and served as its CTO until 2003. In January 2004, he joined the Kyushu Institute of Technology, Iizuka, Japan, where he is currently a Professor. He was the Program Committee Co-Chair of the Sixteenth IEEE Asian Test Symposium and the Eighth IEEE Workshop on RTL and High Level Testing. In addition, he served on the program committees of IEEE Asian Test Symposium (ATS), IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), IEEE Int’l Symposium on Electronic Design, Test, & Applications (DELTA), IEEE Int'l Conf. on Design & Test of Integrated Systems in Nanoscale Technology (DTIS), IEEE Int'l Test Conference (ITC), IEEE Workshop on RTL and High Level Testing (WRTLT), and IEEE Workshop on Defect-Based Testing. His research interests include low-power test generation, high-quality test generation, test compression, fault diagnosis, and testable design. He is the Co-Editor of the book “VLSI Test Principles and Architectures: Design for Testability” (Elsevier, 2006), 32 journal papers, and 60 conference and symposium papers. He is a senior member of the IEEE, a member of the IEICE, and a member of the REAJ.

 

 

 

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53rd IEEE International Midwest Symposium on Circuits and Systems